Soitec and PSMC collaborate on ultra-thin TLT technology for nm-scale 3D stacking [Yahoo! Finance]
SILICON ON INS UNSP/ADR (SLOIY)
NASDAQ:AMEX Investor Relations:
aip.scitation.org/doi/abs/10.1063/1.1558223
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Source: Yahoo! Finance
Bernin (France), June 3, 2025 – Soitec (Euronext – Tech Leaders), a world leader in the design and production of innovative semiconductor materials, today announced a strategic collaboration with Powerchip Semiconductor Manufacturing Corporation (PSMC). Under the collaboration, Soitec will supply PSMC 300mm substrates incorporating a release layer, Transistor Layer Transfer (TLT) ready, to support a new demonstration of advanced 3D chip stacking at the wafer level. This marks the first public announcement of Soitec's TLT technology. The technology is an enabler for next-generation semiconductor designs that allow for more powerful, compact and energy-efficient chips – with potential applications ranging from smartphones, tablets and AI devices to autonomous driving systems. Soitec's Chief Technology Officer and Senior EVP Innovation, Christophe Maleville said: “ At Soitec we are proud to pioneer semiconductor materials that unlock new possibilities in chip design and performanc
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